1. Field of the Invention
The present invention relates to a flexible multi-area memory and an electronic device using this memory. Particularly, the invention relates to a flexible multi-area memory used for an electronic device having a plurality of processors and facing the necessity of reducing the size and weight, such as a mobile phone with a camera function, which is especially suitable for use in the case where each processor is replaced with a different type of processor, and an electronic device using this memory.
2. Description of Related Art
Electronic devices such as mobile phones face the necessity of reducing the size and weight. Recent mobile phones have a camera function, videophone function, and so on in addition to normal communication functions. Such mobile phones have a communication central processing unit (CCPU) for controlling data communication with a wireless base station, an application central processing unit (ACPU) for processing software of applications such as a camera function and ringing melodies function, and a memory for storing various data.
This type of conventional mobile phone has an antenna 1, a wireless communication section 2, a button operation section 3, a CPU 4, a camera section 5, a digital signal processor (DSP) 6, a static random access memory (SRAM) 7, an arbiter 8, an interface (I/F) 9, a gold/gold ball 10, and a synchronous dynamic random access memory (SDRAM) 11, for example, as shown in FIG. 12. The wireless communication section 2 transmits and receives a wireless electric wave W to and from a wireless base station, which is not shown, via the antenna 1. The button operation section 3 is composed of a transmission key, a conversion key of English/Katakana/Kanji/Number, a power on/off key, a cross key for cursor control, an end key, and so on. The CPU 4 functions as the CCPU and also controls the entire mobile phone.
The camera section 5 is composed of a charge coupled device (CCD) camera or the like to take the image in the vicinity of the mobile phone. The DSP 6 functions as the ACPU and processes the image signal shot by the camera section 5. The SRAM 7 is composed of memory cells each of which has six elements consisting of four transistors and two resistors or consisting of six transistors. The SRAM 7 stores data shared by the CPU 4 and the DSP 6, which is image data having been processed by the DSP 6, for example. The arbiter 8 arbitrates simultaneous access from the CPU 4 and the DSP 6 to the SDRAM 11 via the interface 9 so as to avoid conflict. The gold/gold ball 10 makes contacts between the input/output port of the interface 9 and the input/output port of the SDRAM 11. The SDRAM 11 is a double data rate (DDR) type DRAM composed of memory cells each of which has two elements consisting of one transistor and one capacitor. The SDRAM 11 exchanges data with the CPU 4 or the DSP 6 in synchronization with both rise and fall edges of an external clock signal in order to double the data transfer efficiency without increasing the clock frequency.
This type of technique is also disclosed in Japanese Unexamined Patent Application Publication No. 59-129989 (Ikeda). Ikeda teaches a dual-port dynamic random access memory which is composed of 2T-1C memory cells, each consisting of two transfer gates and one capacitor. Each memory cell has two separated access paths, thereby avoiding the exclusive use of a data bus if suitably operated.
The present invention, however, has recognized that the above memory used for a mobile phone has the following problems.
Since the arbiter 8 arbitrates simultaneous access to the SDRAM 11 by the CPU 4 and the DSP 6, it impedes high-speed processing. Further, the CPU 4 and the DSP 6 have different functions, and the capacity of the SDRAM 11 may be too large or too small for the capacity required for each function, which can cause the SDRAM 11 to fail to store necessary data. Further, if the CPU 4 and the DSP 6 are replaced with different types of processors, it is impossible to set the capacity suitable for each function, which also causes the same problem.
Further, though the memory taught by Ikeda can eliminate the exclusive use of a data bus, it is not compatible with high-speed processing or a capacity corresponding to each function of a plurality of processors.